Seminars
Phase Change Memory and its impacts on Memory Hierarchy
Edward Doller, CTO, Numonyx
Wednesday, September 23, 2009
1:00 pm - 2:30 pm
GHC 8102
ABSTRACT:
The goal of this talk is to give attendees a basic idea of the fundamental capabilities of the technology, so that we can have a joint discussion on the most promising applications, given these unique attributes.
Talk Agenda:
Numonyx Background / Why PCM
- Reliability and Scaling
What is PCM, How it works
- Reliability Uniqueness of PCM
- Soft Error rates vs. DRAM
Technology Trends (+/-5yr): (DRAM, NAND,PCM)
- Performance (No Erase)
- Read Access Time/Latency, Read Bandwidth
- Write Access Time/Latency, Write Bandwidth
- Power
- Cost
- Discussion: Potential applications
IO: System Trends in Storage
- IOPS capability on PCIe, vs. SSD/SATA, HDD(magnetics)
NVRAM: Interesting Opportunities in Memory Hierarchy Considerations
- Direct interface support for read, Efficient byte access
- Related Research Areas
- Discussion: Overall discussion on relevant areas of research
to prove out most promising ideas
BIO:
Ed was appointed CTO of Numonyx during its formation in 2008. During his tenure at Intel, he held a variety of positions in the flash memory group before being named CTO in 2004. Prior to joining Intel, Ed held several key positions at IIBM in East Fishkill, N.Y., all in advanced semiconductor memories. Ed has over 24 years of experience in semiconductor memories, holds multiple patents, is a co-author of the IEEE floating gate standard, and is a frequent key note speaker at memory conferences. He received a BS in computer engineering from Purdue University in 1984.
Amdahl's Law in the Multicore Era
Mark D. Hill, Computer Sciences Department, University of Wisconsin-Madison
Joint CALCM/IRHPIT (LANL) video conferenced seminar
Tuesday April 7, 2009
ABSTRACT:
Over the last several decades computer architects have been phenomenally successful turning the transistor bounty provided by Moore's Law into chips with ever increasing single-threaded performance. During many of these successful years, however, many researchers paid scant attention to multiprocessor work. Now as vendors turn to multicore chips, researchers are reacting with more papers on multi-threaded systems. While this is good, we are concerned that further work on single-thread performance will be squashed.
To help understand future high-level trade-offs, we develop a corollary to Amdahl's Law for multicore chips [Hill & Marty, IEEE Computer 2008]. It models fixed chip resources for alternative designs that use symmetric cores, asymmetric cores, or dynamic techniques that allow cores to work together on sequential execution. Our results encourage multicore designers to view performance of the entire chip rather than focus on core efficiencies.
Moreover, we observe that obtaining optimal multicore performance requires further research, both in extracting more parallelism, and making sequential cores faster.
This talk is based on an HPCA 2008 keynote address.
BIO:
Mark D. Hill is professor in both the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin- Madison, where he also co-leads the Wisconsin Multifacet project with David Wood. Mark earned a Ph.D. from University of California, Berkeley. He is an ACM Fellow and a Fellow of the IEEE. His past work ranges from refining multiprocessor memory consistency models to developing the 3C model of cache behavior (compulsory, capacity, and conflict misses).
Storage for Petascale Computing
John Bent, Los Alamos National Lab
Wednesday March 25, 2009
Slides - PDF [5.5M]
ABSTRACT:
The fastest supercomputer in the world right now is Los Alamos National Lab's Roadrunner Petaflop Supercomputer. The process of bringing this machine online and preparing it for users has been ongoing for the past several months. This talk will discuss many of the challenges involved as well as some of LANL's unique solutions. Although the emphasis will be on the scratch storage system, there will be some discussion of the network, the hybrid cell architecture, and the expected workloads. At the end of the talk, there will also be a brief description of several of the presenter's other ongoing research projects.
BIO:
John Bent is a LANL storage researcher who has been heavily involved with the Roadrunner storage system from early planning to intensive troubleshooting during this installation period. John is also leading LANL's data-intensive computing effort, is developing a virtual interposition file system, is working closely with Panasas to debug and design their parallel file system, is collecting and releasing many parallel IO traces, and is mentoring several graduate student projects. John got his PhD in computer science from Wisconsin in 2005 and his bachelors in anthropology from Amherst College in 1995.